FINAL CALL FOR PARTICIPATION

TUTORIALS AT A GLANCE (ON DECEMBER 20)

Tutorial	Speakers	Venue	Time
Dot Net Programming: an Interactive Tutorial	Sunil Sabat (IBM USA)	Silicon Institute of Technology	(Full-day)
Recent Advances in Logic Verification	Dhiraj Pradhan (University of Bristol, U.K)	College of Engineering,bbs	(Half-day)
Embedded Systems: Models, Hardware and OS	D. Mukhopadhyay (Jadavpur University) & S. Majumder (IIIT, Calcutta)	ITER, bbs	(Half-day)
E-Commerce Web Application Security, Sukumar Nandi (IIT Guwahati) & Vivek	Sukumar Nandi (IIT Guwahati) & V. Ramachandran (Cisco Systems)	ISIT,bbs
Fault Diagnosis of Analog Circuits	P. Kabisatpathy (CET, Bhubaneswar)	Vani Vihar, bbs

OUTLINE OF TUTORIALS

TUTORIAL 1: dot Net Programming: an Interactive Tutorial

Sunil Sabat, IBM USA

Abstract

Purpose of the tutorial is to introduce fast growing Microsoft’s .NET framework and programming. The .NET Framework is a development and execution environment that allows different programming

languages & libraries to work together seamlessly to create Windows-based applications that are easier to build, manage, deploy, and integrate with other networked systems. With .NET, Microsoft is finally addressing developers’ cries for help by creating an entirely object-oriented platform. Platform services are now divided into individual namespaces (such as System.Collections, System.Data, System.IO, System.Security, System.Web, and so on), and each namespace contains a set of related class types that allow access to the platform’s services.

Tutorial Topics

¨ What is .NET ( 1.1 and just released 2.0) - Web Programming to Embedded Programming

¨ Essentials of the platform - discuss Forms, Network, Web Elements, Namespaces

¨ Basic Programming Model - focus on object/component programming

¨ Language choice ( VB.NET, C# )

¨ VB.NET Language Features - discuss basic syntax and programming guidelines

¨ Use Visual Studio .NET to program

¨ A VB.NET Console Application - anatomy

¨ A VB.NET Windows Forms Applications - anatomy

¨ A VB.NET Web Application - anatomy

¨ Enterprise Applications Development ( XML, SOAP, WSDL )

¨ Microsoft Solutions Framework - sure path to the success of your IT project

¨ Hands-on Exercises ( 3-5 programs as time permits)

TUTORIAL 2: Recent Advances in Logic Verification

Dhiraj Pradhan, University of Bristol, U.K

Abstract

The tutorial will provide an overview of recent developments as well as basic principles of formal verification techniques including property checking and equivalence checking. Also, it will provide perspective of practical industrial experiences in the use and development of the tools.

The topics are: Design flow, RTL-verification, Simulation-based techniques, coverage metrics and approaches towards coverage-directed stimulus generation, basic concepts of property checking and equivalence checking, combinational equivalence checking, ATPG-based techniques, compare point matching, mitering, don't cares, solver overview (structural verification, BDD-based solvers), Decision Diagrams (BDDs, zBDDs, word-level DDs).

About the Speaker:

Professor Pradhan currently holds a Chair in Computer Science at the University of Bristol (U.K.). Recently, he had been Professor of Electrical and Computer Engineering Department at Oregon State University, Corvallis. Previous to this, Dr. Pradhan had held the COE Endowed Chair Professorship in Computer Science at Texas A&M University, College Station, also serving as Visiting Professor at Stanford University (Calif.). The holder of two patents, Dr. Pradhan has also served as co-author and editor of various books. A Fellow of both ACM and IEEE, Professor Pradhan is also the holder of a Humboldt Prize, Germany. In 1997, Dr. Pradhan was also awarded the '97-'98 Fulbright Flad Chair in Computer

TUTORIAL 3: Embedded Systems: Models, Hardware and OS

D. Mukhopadhyay, Jadavpur University & S. Majumder, IIIT, Calcutta

Abstract:

Over the past decade embedded systems in various architectures and functionalities are finding considerable usage in industries.

This tutorial will deal with the architecture, protocols and hardware of embedded processors and systems. The architecture and the hardware building blocks that go to make an embedded board will be discussed. A review of the architecture of an embedded system and the different protocols for connectivity will be dealt with.

The major hardware components that go to make an embedded board will be taken up and their functionalities explained. The design of embedded processors will be covered introducing the different ISA models. Various types of on-board memory will be introduced and their performance along with memory management of on-board memory will be discussed. Board I/O: serial and parallel, their interfacing and performance will also be taken up.

Discussion on embedded software will start with an introduction to device drivers. The difference between architecture-specific and board–specific drivers will be discussed together with examples of different types of device drivers.

Finally a general discussion on embedded operating systems will be taken up. This will include discussions on process management, scheduling and inter-task communication. Memory management and I/O management at the OS level will also be discussed.

About the Speaker:

D. Mukhopadhyay, obtained his M. Tech and Ph. D. degrees from the Institute of Radiophysics and Electronics, University of Calcutta. He joined the Dept. of Electronics and Telecommunication Engineering, Jadavpur University, as a Lecturer in 1969. During the period from 1975 to 1977, he had been an Assistant Professor in the Dept. of Electrical Engineering, Indian Institute of Technology, Madras, where he worked on a Ministry of Defense project for fabricating high-power, high-frequency p-i-n diodes used as switching elements in high-resolution phased-array radar systems. He re-joined Jadavpur University in 1977 where he became a Professor in 1983.

Professor Mukhopadhyay specializes in semiconductor materials and devices and is known for his work on the high electric-field conduction in compound semiconductors. At Jadavpur University, apart from his teaching and research activities, he had been the principal investigator and co-coordinator in a number of funded projects on ASIC Design, IC Fabrication, Simulation and Modeling of Semiconductor Devices etc.

In recent years, Professor Mukhopadhyay shifted his attention to the Computer Aided Design of Integrated Circuits. With assistance from AICTE and Industries, he set up an Electronic Design Automation (EDA) Laboratory and trained students in this area of industrial importance. He works as the coordinator of the program on "Special Manpower Training Program on VLSI Design" sponsored by the Ministry of Communication and Information Technology. He has delivered several invited talks on “Physics and Modeling Issues in Submicron MOSFETs” and “Low-power Issues in VLSI Design” at conferences and workshops held at various Universities and IITs.

TUTORIAL 4: E-Commerce Web Application Security

Sukumar Nandi, IIT Guwahati &

Vivek Ramachandran, Cisco Systems

Abstract:

The Internet has grown at an exponential rate since it’s inception in the early 1960’s from the ARPANET. The mass usage of the Internet around the Globe has attracted businesses worldwide to setup online trade and commerce outlets to attract a global customer. The race to be “online and connected” and the rush for “time to market” have unfortunately led to security issues taking a backseat. E-Commerce is nowadays the buzz of the day with almost all companies taking a shot at online trading. Companies offer their products online, which can be bought from halfway around the globe at the click of a mouse. Banks have also taken an aggressive lead by bringing their businesses online and allowing customers to transfer millions of dollars around the world with a few mouse clicks. The amount of money being traded on the Internet has not just attracted businesses but also criminals. The Internet has given birth to a new breed of criminal minds who are highly educated, skilled and professional in their approach. Organized crime is plaguing the Internet like never before with these cyber criminals a.k.a Hackers and Crackers targeting Banks and E-Businesses. These hackers exploit vulnerabilities in E-Commerce Applications and steal credit card numbers, bank accounts and even identities for their profit. These malicious activities pose a great risk to E-Commerce and associated businesses with projected losses in millions of dollars caused by a downtime of a few minutes. Our tutorial will focus on discussing the various Security Vulnerabilities in E-Commerce applications mainly E-Commerce Web applications and techniques to secure them and make them hacker proof.

Technical Details: We will divide E-Commerce security into 3 distinct sections:

1. Securing the network where the E-Commerce applications are hosted.

2. Securing the Servers on which the E-Commerce applications are hosted.

3. Securing the E-Commerce application with special stress on E-Commerce Web Application security.

We will provide a detailed discussion on each of the above from two viewpoints viz.

1. How to audit an E-Commerce Security by using penetration testing methodologies and

2. How to secure E-Commerce Applications from being exploited by hackers.

The discussion on “Securing the E-Commerce Network” will consist of the following topics: Network infrastructure basics, Security concerns, Router and Switch Security, Design of a secure network by the usage of Firewalls and Intrusion Detection systems, DDoS protection, Application Intrusion prevention systems, Open Source tools to audit network security from time to time, Google hacking – Using Google for Network Reconnaissance, Commonly made “security mistakes” and the Security best practices for the Network.

The discussion on “Securing the Server” will consist of the following topics: Server Security, Patch Management, Hardening the OS, Hardening individual Service Configurations, Host based Intrusion Detection and Prevention Systems and the Security best practices to be followed by server administrators.

The discussion on “Securing the E-Commerce Application” will consist of the following: E-Commerce Application Basics, Application Security Basics, CGI Security, PHP Security, Secure Code Design-Implementation-Testing, Web Browser Vulnerabilities, Brute forcing HTTP Authentication, HTTP and SSL man-in-the-middle Attacks, Form Input Manipulation, Hidden Field Manipulation, Parameter Tampering, Cookie Poisoning, Database Security, SQL Injection, Command Injection, Cross Site Scripting, Cross Site Tracing, Malaware detection & removal and security best practices for programming, testing and deploying E-Commerce applications.

If allowed, we can show some practical demonstrations of how E-Commerce applications are compromised by hackers on the Internet and how to secure them. We will get our own Laptop for the demonstration so that the organizers are not burdened with providing extra computers and software.

About the Speakers:

Professor Nandi is the Head of Department of Computer Science, Indian Institute of Technology, Guwahati (IIT-G). He is also the Head, Centre for Educational Technology and a senior member of the IEEE. He has worked as visiting Senior Fellow at Nanyang Technology University, Singapore. He has more than 85 publications in various international journals and conference proceedings in diverse fields of computer science ranging from computer security, VLSI, QoS to Wireless, to his credit. He is the coauthor of the celebrated book “Theory and Applications of Cellular Automata” published by IEEE Computer Society. He has also successfully executed several projects sponsored by the Department of Science and Technology and Ministry of Human Resource and Development of the Govt. of India. He has provided consultancy to companies like the General Insurance Company in Mumbai, Assam Petrochemicals Limited etc and to Academic institutions such as Helsinki University of Technology in Finland. He has also successfully guided two PhD students and six are doing research under his guidance. His areas of interests are Wireless Networks, Computer and Network security etc.

Vivek Ramachandran is a Development Engineer in Cisco Systems, Inc. He works on enterprise security features such as 802.1x (Basic 802.1x and LAN-port 802.1x used in Cisco’s Network Admission Control solution) and Port Security on the Catalyst Switches. He has various enhancements to the 802.1x implementation on Cisco’s Catalyst series of switches to his credit. Vivek, an Electronics and Communication Engineer graduated from the Indian Institute of Technology, Guwahati (IIT-G). As part of his thesis, he had worked extensively on E-Commerce Security, Web Application security, Layer 2 and Layer 3 security, Anomaly based network intrusion detection systems, Wireless Lan Security and on Distributed Denial of Service detection and mitigation techniques. Vivek has given many talks on Networking, Network Security and Network Programming to students of IIT Guwahati. These talks were arranged by the IIT-G Networking Society.

TUTORIAL 5 Fault Diagnosis of Analog Circuits

P. Kabisatpathy, CET, Bhubaneswar

Abstract :

The field of integrated circuit (IC) has undergone remarkable changes over the past decade. ICs incorporating both digital and analog function have become more and more popular in semiconductor industry. These combined circuits are called “Mixed Signal Circuits”. Fault diagnosis and testing of IC has grown into a special field of interest in the semiconductor industry. The methodologies of testing digital circuits are well established. However, the methodologies for fault diagnosis of analog ICs are relatively unexplored. Some of the reasons for this under development are lack of proper fault model of the devices operating in the continuous time domain, multiple value of the signal at each node of the circuit, etc.

This tutorial on Fault Diagnosis of Analog Integrated Circuits is primarily intended for students at graduate level and practicing field engineers in the area of analog and mixed-signal IC testing. The prime objective is to provide an insight into the different fault diagnosis techniques of analog ICs. The tutorial is organized in six sections.

Section 1 is the introductory section incorporating the basic concepts of analog fault diagnosis. Both simulation-after-test and simulation-before-test have been discussed.

Section 2 introduces failure modes and mechanisms for electronic components, analog fault models adopted for various analog devices including the catastrophic fault models of resistor, capacitor, diode, BJT and MOSFET and some important types of approximation models those could be used in modeling the analog circuit under test.

The choice of optimum test stimulus is the key to success in fault diagnosis. All classical and state-of-art techniques of test stimulus generation have been discussed in Section 3 including the more recent topics like the delta-sigma signal generation and the pseudo-random noise (PRN) generation.

Section 4 describes the fault diagnosis methodology covering fault diagnosis procedure, fault dictionary techniques, DSP based techniques and the model based observer scheme. This section also describes in detail the application of the model-based observer scheme for detection and identification of faults in stand-alone as well as embedded analog ICs. The integrated circuit, particularly the operational amplifier (op-amp) is the most used building block of analog signal processing. This section presents a detailed overview of fault diagnosis of op-amps (at the device or component level) using model based observer technique. Simulated results for the fault in bipolar MOS op-amps are given here. Besides, fault diagnosis of simple analog system-on-chip (SOC) is also presented. An experimental test set-up for fault detection and diagnosis in analog ICs and SOCs, is also presented.

Section 5 discusses briefly the design-for-testability (DfT) approaches and the development of built-in self-test (BIST) facilities in analog ICs.

Section 6 is the concluding section of the tutorial. The limitations of analog integrated circuit fault diagnosis techniques along with the scope for future are noted.

Reference: P. Kabisatpathy, A. Barua and S. Sinha, “Fault Diagnosis of Analog Integrated Circuits”, Springer, P.O. Box 17 3300 AA Dordrecht, The Netherlands.

MAIN PROGRAM

VENUE: Institute of Physics, Bhubaneswar

DECEMBER 21, 2005

08:00 -14:00 REGISTRATION

9:00 - 10:00 Inaguration

10:00 - 10:10 Welcome of participants

10.10 – 11.00 INAUGURAL KEYNOTE SPEECH

Dhiraj Pradhan, University of Bristol, UK

11:00 – 11:30 Tea Break

11:30 – 13:00 SESSION IA- Distributed Computing

A Parallel Algorithm for Dynamic Slicing of Distributed Java Programs in non-DSM Systems D P Mohapatra, R Mall, R Kumar

Parallel Program Scheduling in a Heterogeneous Wireless Mobile Computing Environment E.Ilavarasan, P.Thambidurai

Mobile Agent Location Management in Global Networks R. B. Patel, N Mastorakis, K. Garg

Parallel Session

11:300 – 13:00 SESSION IB- Internet & QOS

Developing online instruction: Information Technology and Education in the Global Context, H Najjari

Bleeding Edge DDoS Mitigation Techniques for ISPs, V Ramachandran, S Nandi

Bandwidth Efficient Resource Allocation Scheme for Wireless Video Transmission, G. Sivaradje, S.Anbarasan,P. Dananjayan

13.00 – 14:15 Lunch Break

14:15P - 15:45 Session 2A- Networks and Protocols

Dependency Sensitive Distributed Commit Protocol, U. Shanker, M. Misra, A.K.Sarje

A multistage interconnection network with real time fault detection and avoidance capabilities, M Saha, I Sengupta

A Pattern Matching Based Approach towards Phylogenetic Networks with Constrained Recombination, M.A.H Zahid, A Mittal, R.C. Joshi

Parallel Session

14:15P - 15:45 Session 2B- Software Engineering

Software Complexity Assessment Using Statistical Technique: Towards Software Testing Effort Estimation, P. Dhavachelvan, N. Sivakumar, N. Saravanan,, S. Sampath Kumar, V.S.K.Venkatachalapathy

Software Testing – A Graph Theoretic Approach, V Bhattacherjee, D Suri, P K Mahanti

Measuring User’s Role to Assess Organization Preparedness in a Systems Acquisition Life Cycle: A Cognitive Framework, H.K. Misra, B. Mohanty

15.45 – 16.05 Tea Break

16:05 - 17:05 Session 3A- Networks and Security

Web Document Classification Based on Extended Rough set (short), Gaoxiang Yi, Heping Hu

Authenticating Business Documents using J_HASH (short), U K Ray, S Das Gupta

A Pair of Symmetric Block Ciphers For The Secure Transmission of a File (short), V.U.K Sastry, V.Janaki

Data Fusion: A Tool to Gather Digital Evidence- Suneeta Satpathy, Sateesh Kumar Pradhan, and Avijit Kar

Parallel Session

16:05 - 17:05 Session 3A- Data Mining & Optimization

Framework for Detection of Commercial by Employing Cellular GP (short), Manish Manoria, N Saxena

Redundancy Elimination Using Hash Based Value Numbering (short), V. Vijay Kumar, K.V.N.Sunitha

Parallel Visual Data Mining (short), L.Suresh ,Madhusudan.G

An Interface for Converting Rules Generated by C4.5 to the Most Suitable Format for Genetic Algorithm- B. K. Sarkar, Kanwalijeet Sachdev, Swaraj Bharti, and Amit Bhaskar

17:05 PM – 18:15 PM Panel Discussion:

Challenges to Indian IT Industry Today

Panelists: TBA

DECEMBER 22, 2005

9:00 – 10:00 Invited Talk1

Data Driven Controller Synthesis and Design: New Results

Shankar P. Bhattacharyya, Texas A & M University

10:10- 11:10 Session 4A-Algorithms and Computability

Generation of L-System string from Ramification Matrix, A.K.Bisoi, S.N.Mishra, S.Mishra

Mapcode Computability, Arindama Singh

Parallel Session

10:15 -11:15 Session 4B - Network Protocols

Security Analysis of 802.1X Protocol For Wireless Local Area Networks, D Nayak, D.B.Phatak, V.P. Gulati

Performance Analysis of 802.11 MAC & Time Bound Medium Access Control (TBMAC) Protocol for Adhoc Wireless Network, G. Saikia & D. Goswami

SIP : An Innovative Approach for Seamless Integration in 4G All IP Heterogeneous Wireless Networks-Biswajit Brahma and Ajit Kumar Das

11:10 – 11:30 Tea Break

11:30 – 13.00 Session 5A- Logic, Algorithms & IT in Society

An Algorithm for computing Prime Implicates in 1^st order Logic, M.K. Rout, A. Singh

An Algorithm for Efficient Search for a range of keys in B+ Trees, J. Shiva Prasad, B.K. panigrahy

Reasoning Through Bayesian Modelling , R K Mohanty, D. Rodriguez

Parallel Session

11:30 – 13.00 Session 5B- Internet & Security

Improving Web Performance through Hierarchical Caching & Content Aliasing, S B Patil, D B Kulkarni, S Shere, A K Tripathy

A Research Paradigm for Analysis of TCP SYN Flood And UDP Flood DDoS Attacks, J. S. Bhatia, R. K. Sehgal

A Bayesian-CHI Square Approach to Junk Mail Filtering, Rajesh T , Arun K Pujari

13.00 –14.15 Lunch Break

14:15 – 15:45 Session 6A: Computer Vision

Retrieving Video in Wavelet Compressed Domain, Navajit Saikia ,Prabin K. Bora

Fractal image compression with edge detection, M.L.Valarmathi, K.Anbumani

Development of GA Based Adaptive Techniques for non-linear identification, G. Panda, B. Majhi, D. Mohanty, A. Choubey

Parallel Session

14:15 – 15.45 Session 6B: Networks & protocols

Active Replication to Improve the Dependability of a Dual Redundant System, J. Chattopadhyay, Mazumdar

Extended Varietal Hypercube - A Fault-tolerant Interconnection Topology for Parallel Systems, C.R. Tripathy, R K Dash

A Hardware Aceelerator for Controlling Access to multiple Unit Resource in safety/Time critical Systems, M. Marchand, P. Sinha

15:45 – 16:00 Tea Break

16:00 – 17:00 Session 7A: Computer Vision

Decision Directed Median Filter , B. Majhi, P.K. Sa, G. Panda

MUSIG and MUBET guided PSONN based color object extraction: A Comparative Study, S Bhattacharyya, P Dutta, U Maulik

Parallel Session

16:00 – 17:00 Session 7B: Natural Language Processing

Formant Analysis of Vowels in Emotional States of Oriya Speech Across Gender, S Mohanty, S Swain, R Mishra

Machine Recognition of Printed Malayalam Characters, Roshni, Dr Revathy, S Beevi

17:00 - 17:45 Invited Talk 2

Chitta Baral, Arizona State University, USA

18:00 – 19:00: OITS Business Meeting

DECEMBER 23, 2005

9:00 – 10.00 Invited Talk 3 “Coverage, Connectivity and Routing Problems in Networks”

Arunabh Sen, Arizona State University, USA

10:10-11:10 Session 8A: Bioinformatics

Efficient DNA Fragment Extraction (short), S Silakari, A Sugandhi

Predicting Secondary Structure of RNA using Correlation Framework , Ravi Gupta,Ankush Mittal, Sumit Gupta

Parallel Session

10:10-11:10 Session 8B: Language Processing & AI

Question Answering System based on Paninian Framework: A case study over Oriya Language (short)Chinmaya Kumar Swain

Churn Modeling in Personal Banking using Decision Trees (short), V. Visweswar,, V. Ravi , P. Radha Krishna, A. Sharma, G. Priyadarshi. R. K. Pati, R. Sahu,D. Singh

Designing Multiple Star Schema from XML Scheme (short) P. Pahwa, N. Parimal

11.10 – 11.30 Tea Break

11:30-13:00 Session 9A: Internet, Network Protocol & Architecture

Virtual Topology Design in WDM Optical Networks Using Multi-Objective Optimization, B Karki, A Paul, R Dutta

System-On-Chip (Soc) Test With Mixed-Signal And Analog Cores, S R. Das, J Zakizadeh, M H. Assaf, E M. Petriu, M Sahinoglu

An Efficient Protocol for Certificate Path Validation, V. Valli Kumari, KVSVN Raju

Parallel Session

11:30-13:00 Session 9B: Scientific Computing

To Be Announced

13.00 – 14.30 Lunch Break

2:30 – 3:15 Invited Talk 4 Service Convergence and Optical Ethernet - Scaling from LAN to WAN

Sukant Mohapatra, Lucent Technology, USA

15:15 -15:35 Tea Break

15:35-17:10 Session 10A: Logic, Algorithms & Architecture

Breaking Propositional Logic Based Cryptosystem Using Networks of Evolutionary Processor with Parallel String Rewritting Rules, A Choudhary , K Krithivasan

Reconfigurable digital FIR filter for FPGA mplementation - A study with different multiplier architectures, Sunil Budumuru ,R.K.Singh

High Speed Hardware Units for Efficient Performance of Modified Montgomery Multiplication, H Thapliyal ,S Kotiyal, M.B Srinivas

Parallel Session

15:35-17:10 Session 10B: Network Topology and Routing

Self-Stabilizing Ad hoc On-demand Distance Vector Routing in Mobile Ad hoc Network, S Padhy, D Goswami

Wavelength Assignment in a Ring Topology for Wavelength Selective WDM Optical Networks, Amit Shukla, L. P Singh, R Datta

Shared Path Protection in DWDM Mesh Networks, D Mandal, B Mitra

17:15-17:30 Best Paper Award Ceremony and Closing

REGISTRATION PARTICULARS FOR CIT2005

REGISTRATION FEES:

1. Participants from Educational Inst inside India: Rs.2000/-

2. Participants from Industry inside India: Rs.3000/-

3. Participants from outside India: US$200/-

4. Special categories: (i) OITS members can avail a discount of 50%.

5. Limited financial support for registration may be available for students depending on funds. For this purpose they may apply to S Padhy, General Chair, with full particulars.

6. Payments may be made to `cit2005' as bankdraft/crossed cheque.

(g) Along with registration particulars, it may be dispatched in the address: Sateesh Pradhan, Organising Chair, Department of Computer Science, Utkal University, Vani Vihar, Bhubaneswar 751004, INDIA

The registration fees entitles the registrant to copy of the proceedings material, kitbag, lunches, conference banquet, tea/coffee during breaks and participation in all the technical sessions.

PARTICULARS FOR REGISTRATION:

(a) NAME

(b) AFFILIATION

(d) Particulars of Bank Draft/ crossed cheque, such as amount, date, bank, number, payable to `cit2005'.

(g) Signature and Date.

FOR ADVANCE REGISTRATION:

Besides the hard copy, please send an email regarding the above to the Organising Chair (to whom the hard copy is being sent) sateeshind@yahoo.com. Participants paying in US dollars or outstation checks may preferably do advance registration since it takes some time for these checks to get encashed.

CONFERENCE VENUE & HOTEL ACCOMMODATION

Date: 20.12.2005; All tutorials are held at different local institutions as announced

Dates: 21 - 23, December, 2005: Academic programs of Conference Venue for Academic programs: Institute of Physics Campus. The spot registration will also be possible only by request. All the authors who attends the conference must register in advance. Papers that found with out any of its authors registered will be droped from the conference program.

CONTACT PERSONS AT BHUBANESWAR

S Padhy, Utkal Univ, General Chair

Department of Mathematics, Utkal University,

Vani Vihar, Bhubaneswar 751004, INDIA.

E-mail: spadhy04@yahoo.co.in

Ph. No- 9437204666 (M)

S Pradhan, Utkal Univ, Organising Chair,

Department of Computer Science, Utkal University,

Vani Vihar, Bhubaneswar 751004, INDIA.

E-mail: sateeshind@yahoo.com

Ph. No- 9437001231 (M)

A K Das, Tutorial Chair

E-mail: ajitmita@rediffmail.com

Ph.No.- 9861066366 (M)

Prayag Prasad Mishra

E-mail: prayagk_2000@yahoo.com

Ph. No.- 9861092623 (M)

· Silicon Institute of Technology(SIT), Bhubaneswar

INTRODUCTION

Topics of interest includes

Keynote Speaker		Date	Time
Dhiraj Pradhan, University of Bristol, U.K		Dec. 21	10:00 AM

Topic	Speaker	Date	Time
Data Driven Controller Synthesis and Design: New Results	Shankar P. Bhattacharya, Texas A & M Univ. USA	Dec. 22	9:00-10:00
Invited Talk (sub not available)	Chitta Baral, Arizona State University, USA	Dec. 22	17:00 - 17:45
Coverage, Connectivity and Routing Problems in Networks	Arunabh Sen, Arizona State University, USA	Dec. 23	9:00-10:00
Service Convergence and Optical Ethernet -Scaling from LAN to WAN	Sukant Mohapatra, Lucent Technology, USA	Dec. 23	14:30 – 15:15